SW/HW CoSim That Sticks: Three Re-useable Practical Patterns

Aug 28, 2025

In this blog I discussed practical patterns for pre-silicon SW/HW co-simulation. I walk through three co-sim approaches—each at a different level of control and abstraction—with working examples using a simple ready/valid pipelined adder as the DUT. If you’re exploring co-simulation or pre-silicon verification, give it a look. 

https://embeddedville.hashnode.dev/swhw-cosim-that-sticks-three-re-useable-practical-patterns

SW/HW Co-Sim Stack Design for RISC-V

Aug 10, 2025

In this blog I demonstrated a SW/HW Co-simulation stack that couples unicorn ISS, SystemVerilog testbench and DPI-C bridge level for RISC-V firmware verification. This stack accelerates early-stage software/hardware co-verification in the pre-silicon stage:

https://embeddedville.hashnode.dev/swhw-co-simulation-stack-design

FPGA Prototyping in HLS C++ (Part 3)

Apr 06, 2025

In this blog of my HLS blog series,  I discussed the HLS application development lifecycle, using the RGB2YCbCr project as an example. In addition to a detailed exploration of the RGB2YCbCr development, I also share my perspectives on HLS C++ versus HDL coding in FPGA IP core design. Follow the link below to check the full details of the blog:

https://embeddedville.hashnode.dev/fpga-prototyping-in-hls-c-part-3

FPGA Prototyping in HLS C++ (Part 2)

Apr 05, 2025

In this blog of my HLS blog series,  I dived into the key features of SmartHLS C++, custom C++ libraries, and essential SmartHLS pragmas. These serve as the foundational elements for programmatically building an FPGA IP core in HLS C++.  Follow the link below to check the full details of the blog:

https://embeddedville.hashnode.dev/fpga-prototyping-in-hls-c-part-2

FPGA Prototyping in HLS C++ (Part 1)

Feb 08, 2025

Although FPGA design has been evolving rapidly in the last decade, RTL-based design using Verilog/VHDL remains the mainstream approach for production and high-performance applications. However, HLS (High-Level Synthesis) adoption is increasing, especially in AI, networking, and rapid prototyping. In this blog of my HLS blog series,  I discussed what is high level synthesis and took Microchip SmartHLS example to explain how HLS works as well as the way to use SmartHLS. Follow the link below to check the full details of the blog:

https://embeddedville.hashnode.dev/fpga-prototyping-in-hls-c-part-1

Deep Dive into CPU Usage Calculation on Linux

Jun 02, 2022

It is undoubtedly to say that insufficient system resources such as storage, memory or CPU can greatly affect an application’s performance, so monitoring these components is a must for any high-performing yet resource-constraint systems. Unlike disk and memory, monitoring the CPU usage on a Linux system isn’t straightforward, and the use of the CPU usage and the CPU load is drastically different. In this article, I will dive into understanding and displaying CPU metrics in a human-readable format.  Follow the link to check the full details:

https://embeddedville.hashnode.dev/a-deep-dive-into-the-cpu-usage-calculation-on-linux