My journey as an engineer is fueled by a deep passion for low-level computer engineering. The ability to work across both firmware and digital hardware empowers me to tackle complex real-world challenges with innovative solutions.
My guiding principle is simple—take ownership and make a meaningful impact. This portfolio showcases my past work alongside personal projects that reflect my expertise and curiosity.
09/2021 - 06/2023 , Boulder Flagship Campus
Specialized in embedded system engineering, under Electrical Engineering Department, with CGPA of 3.97/4.00.
Key Area
Real-Time Embedded System (RTOS)
Embedded System Architecture
Low-power Firmware
Embedded Computer Vision
Embedded Linux Development
09/2013- 06/2018 , St. George Campus
Enrolled in computer engineering under Electrical, Computer Engineering Department, with CGPA of 3.45/4.00.
Key Area
Embedded Software
Digital Hardware
Computer Network
03/2025 - Present, Toronto, Canada
Designed and implemented a fully streaming CLAHE IP core in HLS C++ for real-time image and video processing
Engineered a CoaXPress-based video streaming solution, integrating HLS C++ processing cores with a Verilog CoaXPress-to-AXI adapter and validating the end-to-end flow in a SystemVerilog testbench
Implemented interrupt-driven SoC: RTL/HLS cores interrupt the RISC-V MSS, handled by C ISRs
Added reusable HLS C++ functions for vision, DSP, and motor control to the fpga-hls-libraries repo
Crafted and debugged firmware for RISC-V softcore microprocessors on PolarFire FPGA platforms
Contributed the automated SoC flow feature for the RV32 RISC-V MSS in SmartHLS2025.1
Led IP integration and system-level verification of mixed RTL and HLS designs using UVM
06/2023 - 03/2025, Toronto, Canada
Engineered high-performance C++ accelerator drivers for FPGA IPs in both bare-metal and Linux environments
Prototyped FPGA architectures in HLS C++, including optimized DSP filter implementations
Streamlined Python-based HLS IP generation and integration for BeagleV-Fire on Microchip FPGAs
Built Device Tree bindings and a DMA Linux driver for FPGA‐DDR data transfers
Executed on-chip debugging of FPGA-based SoC applications using OpenOCD, GDB, and hardware instrumentation
Developed a Python-based framework for heterogeneous FPGA device management across multiple platforms
Enhanced HLS toolchain throughput with Python and C++ extensions, significantly reducing synthesis times
Contributed C++ system software libraries for standardized SoC IP interfacing and control
12/2019 - 06/2021 , Toronto, Canada
Developed Python-based, multi-threaded embedded applications to support real-time data processing
Led the design and implementation of continuous integration infrastructure on the TeamCity platform
Designed and implemented Linux device drivers and ported firmware in C/C++
Conducted system performance instrumentation and debugging to optimize overall efficiency
Extended Board Support Packages by customizing U-Boot and the Linux kernel
Directed the development of custom Linux distributions using the Yocto Platform
Embedded Engineer - JetIO Technology Corporation
06/2018 - 11/2019, Toronto, Canada
Spearheaded RTL design of a dual-image bootloader in Verilog
Performed SystemVerilog-based RTL IP verification and on-chip debugging using hardware instrumentation
Conducted real-time performance characterization and statistical analysis of NAND flash behavior
Developed an embedded C firmware testbench for validating FPGA-based flash controllers
Contributed to the creation of a Jenkins-based continuous integration platform for automated embedded testing
Embedded Software Engineer Intern - Evertz Microsystems Ltd
06/2016 - 07/2017, Burlington, Canada
Achieved a 50% performance boost by optimizing the XMODEM protocol implementation
Engineered multi-threaded, real-time firmware in embedded C using FreeRTOS
Utilized oscilloscopes and other instrumentation tools to troubleshoot firmware and hardware issues
Implemented HAL drivers for I²C, SPI, and MDIO protocols on bare-metal microprocessors
